DSP56857 datasheet(285/662 Pages) FREESCALE

285 / 662 page

Transmission Data

Serial Peripheral Interface (SPI), Rev. 4

Freescale Semiconductor

11-15

Figure 11-9. Transmission Start Delay (Master)

11.8 Transmission Data

The double-buffered Data Transmit Register (SPDTR) allows data to be queued and transmitted.

For a SPI configured as a master, the queued data is transmitted immediately after the previous

transmission has completed. The SPI Transmitter Empty (SPTE) flag indicates when the transmit

data buffer is ready to accept new data. Write to the SPDTR only when the SPTE bit is high.

Figure 11-10 illustrates the timing associated with doing back-to-back transmissions with the

SPI (SCLK has CPHA: CPOL = 1:0).

Note:

Figure 11-10 assumes 16-bit data lengths and the MSB shifted out first.

SPDTR

Initiation Delay

BUS

MOSI

SCLK

(CPHA = 1)

SCLK

(CPHA = 0)

SCLK CYCLE

NUMBER

MSB

Bit 15

CLOCK

Write

to SPDTR

EARLIEST LATEST

(SCLK = INTERNAL CLOCK

÷ 2;

EARLIEST

LATEST

2 Possible START Points)

(SCLK = INTERNAL CLOCK

÷ 8;

8 Possible START Points)

EARLIEST

LATEST

(SCLK = INTERNAL CLOCK

÷ 16;

16 Possible START Points)

EARLIEST

LATEST

(SCLK = INTERNAL CLOCK

÷ 32;

32 Possible START Points)

Write

to SPDTR

Write

to SPDTR

Write

to SPDTR

BUS

CLOCK

Bit 14

BUS

CLOCK

BUS

CLOCK

BUS

CLOCK

Initiation Delayfrom Write SPDTR to Transfer Begin

Write

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