DSP56857 datasheet(277/662 Pages) FREESCALE

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Operating Modes

Serial Peripheral Interface (SPI), Rev. 4

Freescale Semiconductor

11-7

11.6 Operating Modes

The SPI has two operating modes:

•Master

•

Slave

An operating mode is selected by the SPMSTR bit in the SPSCR as follows:

•

SPMSTR = 0 Slave mode

•

SPMSTR = 1 Master mode

Note:

The SPMSTR bit should be configured before enabling the SPI, setting the SPE bit in

the SPSCR. The master SPI should be enabled before enabling any slave SPI. All slave

SPIs should be disabled before disabling the master SPI.

11.6.1 Master Mode

The SPI operates in Master mode when the SPI master bit, SPMSTR, is set.

Note:

Configure the SPI module as master or slave before enabling the SPI. Enable the

master SPI before enabling the slave SPI. Disable the slave SPI before disabling the

master SPI.

Only a Master SPI module can initiate transmissions. With the SPI enabled, software begins the

transmission from the Master SPI module by writing to the SPI Data Transmit Register (SPDTR).

If the Shift register is empty, the data immediately transfers to the Shift register, setting the SPI

Transmitter Empty (SPTE) bit. The data begins shifting out on the MOSI pin under the control of

the SPI Serial Clock (SCLK).

The SPR2, SPR1 and SPR0 bits in the SPSCR register, control the baud rate generator and

determine the speed of the Shift register. Through the SCLK pin, the baud rate generator of the

master also controls the Shift register of the slave peripheral.

As the data shifts out on the MOSI pin of the master, external data shifts in from the slave on the

master’s MISO pin. The transmission ends when the Receiver Full (SPRF) bit becomes set. At the

same time the SPRF becomes set the data from the slave transfer to the Receive Data register. In

normal operation, SPRF signals the end of a transmission. Software clears SPRF by reading the

SPI Data Receive Register (SPDRR). Writing to the SPI Data Transmit Register (SPDTR) clears

the SPTE bit.

Figure 11-3 is an example configuration for a Full-Duplex Master-Slave Configuration. Having

the SS bit of the Master DSC held high is only necessary if MODFEN = 1. Tying the Slave DSC

SS bit to ground should only be executed if CPHA = 1.

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