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DSP56857 bảng dữ liệu(PDF) 273 Page - Freescale Semiconductor, Inc |
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DSP56857 bảng dữ liệu(HTML) 273 Page - Freescale Semiconductor, Inc |
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273 / 662 page ![]() Features Serial Peripheral Interface (SPI), Rev. 4 Freescale Semiconductor 11-3 11.1 Introduction This section describes the Serial Peripheral Interface (SPI) module available on each chip, with the exception for the 56855. The module allows full-duplex, synchronous, serial communication between the Digital Signal Controllers (DSC) and peripheral devices, including other DSCs. Software can poll SPI status flags or SPI operation can be interrupt driven. This block contains four 16-bit memory mapped registers for control parameters, status, and data transfer. 11.2 Features Features of the SPI module include: • Full-duplex operation • Master and slave modes • Double-buffered operation with separate transmit and receive registers • Programmable length transmissions (2 to 16 bits) • Programmable transmit and receive shift order (MSB first or last bit transmitted) • Eight master mode frequencies (maximum = bus frequency/21) • Maximum slave mode frequency = bus frequency • Clock ground for reduced Radio Frequency (RF) interference • Serial clock with programmable polarity and phase • Two separately enabled interrupts — SPRF (SPI Receiver Full) — SPTE (SPI Transmitter Empty) • Mode Fault Error flag with interrupt capability • Direct Memory Access (DMA) capability for both the transmitter and receiver • Wired OR mode functionality to enabling connection to multiple SPIs • Overflow Error Flag with interrupt capability 1. This frequency may be further limited by the GPIO function. |
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