DSP56857 datasheet(245/662 Pages) FREESCALE

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Functional Description

Serial Communications Interface (SCI), Rev. 4

Freescale Semiconductor

10-9

2. Clear the Transmit Data Register Empty (TDRE) flag by first reading the SCI Status

3. Repeat step 2 for each subsequent transmission.

Modifying the TE bit from 0 to a 1 automatically loads the Transmit Shift Register with a

preamble of 10 logic 1s (if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control

logic automatically transfers the data from the SCI Data Register into the Transmit Shift Register.

A Logic 0 start bit automatically goes into the least significant bit position of the Transmit Shift

Hardware supports odd or even parity. When parity is enabled, the Most Significant Bit (MSB) of

the data character is replaced by the parity bit.

The Transmit Data Register Empty (TDRE) flag in the SCI Status Register (SCISR) becomes set

when the SCI Data Register transfers a character to the Transmit Shift Register. The TDRE flag

indicates when the SCI Data Register can accept new data from the internal data bus. If the

Transmitter Empty Interrupt Enable (TEIE) bit in the SCI Control Register (SCICR) is also set,

the TDRE flag generates a transmitter interrupt request. If TDE is enabled, the DMA request will

suppress the TDRE interrupt and a DMA request will be made instead.

When the Transmit Shift Register is not transmitting a frame and TE = 1, the TXD pin goes to the

idle condition, Logic 1. If, at any time, software clears the TE bit in the SCI Control Register

(SCICR), the transmitter relinquishes control of the port I/O pin upon completion of the current

transmission causing the TXD pin to go to a HighZ state.

If software clears TE while a transmission is in progress (TIDLE = 0), the frame in the Transmit

Shift Register continues to shift out. Then transmission stops even if there is data pending in the

SCI Data Register. To avoid accidentally cutting off the last frame in a message, always wait for

TDRE to go high after the last frame before clearing TE.

To separate messages with preambles with minimum idle line time, use this sequence between

messages:

1. Write the last character of the first message to the SCIDR.

2. Wait for the TDRE flag to go high, indicating the transfer of the last frame to the Transmit

Shift Register.

3. Queue a preamble by clearing and then setting the TE bit.

4. Write the first character of the second message to the SCIDR.

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