DSP56857 datasheet(248/662 Pages) FREESCALE

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Functional Description

5685X Digital Signal Controller User Manual, Rev. 4

10-12

Freescale Semiconductor

10.6.4.3 Data Sampling

The receiver samples the RXD pin at the RT clock rate. The RT clock is an internal signal with a

frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock illustrated in

Figure 10-6 is resynchronized:

•

After every start bit

•

After the receiver detects a data bit change from Logic 1 to Logic 0 (after the majority of

data bit samples at RT8, RT9, and RT10 returns a valid Logic 1 and the majority of the next

RT8, RT9, and RT10 samples returns a valid Logic 0)

To locate the Start bit, data recovery logic does an asynchronous search for a Logic 0 preceded by

three logic 1s. When the falling edge of a possible Start bit occurs, the RT clock begins to count

to 16.

Figure 10-6. Receiver Data Sampling

To verify the Start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and

RT7. Table 10-7 summarizes the results of the Start bit verification samples. If the Start bit

verification is not successful, the RT clock is reset and a new search for a Start bit begins.

Table 10-7. Start Bit Verification

RT8, RT9, and RT10

Samples

Data Bit

Determination

Noise

Flag

000

Yes

001

Yes

010

Yes

011

100

Yes

101

110

111

RESET RT CLOCK

SAMPLES

RT CLOCK

RT CLOCK COUNT

START BIT

RXD

START BIT

QUALIFICATION

START BIT

DATA

SAMPLING

LSB

VERIFICATION

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