DSP56857 datasheet(246/662 Pages) FREESCALE

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Functional Description

5685X Digital Signal Controller User Manual, Rev. 4

10-10

Freescale Semiconductor

10.6.3.3 Break Characters

Writing a Logic 1 to the send break bit SBK in the SCI Control Register (SCICR) loads the

Transmit Shift Register with a break character. A break character contains all logic 0s and has no

start, stop, or parity bit. Break character length depends on the M bit in the SCI Control Register

(SCICR). As long as SBK is at Logic 1, transmitter logic continuously loads break characters into

the Transmit Shift register. After software clears the SBK bit, the Shift register finishes

transmitting the last break character and then transmits at least one Logic 1. The automatic Logic

1 at the end of the last break character guarantees the recognition of the Start bit of the next

frame.

The SCI recognizes a break character when a start bit is followed by eight or nine Logic 0 data

bits and a Logic 0 where the Stop bit should be. Receiving a break character has these effects on

SCI registers:

•

Sets the Framing Error (FE) flag

•

Sets the Receive Data Register Full (RDRF) flag

•

Clears the SCI Data Register (SCIDR)

•

May set the Overrun (OR) flag, Noise Flag (NF), Parity Error (PE) flag, or the Receiver

Active Flag (RAF). Please see the SCI Status Register in Section 10.9.4.

10.6.3.4 Preambles

A preamble contains all logic 1s and has no start, stop, or parity bit. A preamble length depends

on the M bit in the SCI Control Register (SCICR). The preamble is a synchronizing mechanism

initiating the first transmission begun after modifying the TE bit from 0 to 1.

If the TE bit is cleared during a transmission, the TXD pin becomes idle after completion of the

transmission in progress. Clearing and then setting the TE bit during a transmission queues a

preamble to be sent after the frame currently being transmitted.

Note:

Toggle the TE bit for a queued preamble when the TDRE flag becomes set and

immediately before writing the next character to the SCI Data Register.

When queueing a preamble, return the TE bit to Logic 1 before the stop bit of the

current frame shifts out to the TXD pin. Setting TE after the stop bit appears on TXD

causes data previously written to the SCI Data Register to be lost.

10.6.3.5 Receiver

Figure 10-5 explains the block diagram of the SCI receiver with detailed discussion of the

receiver function in the following paragraphs.

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