DSP56857 datasheet(247/662 Pages) FREESCALE

247 / 662 page

Functional Description

Serial Communications Interface (SCI), Rev. 4

Freescale Semiconductor

10-11

10.6.4 SCI Receiver Block Diagram

Figure 10-5. SCI Receiver Block Diagram

10.6.4.1 Character Length

The SCI receiver can accommodate either 8- or 9-bit data characters. The state of the M bit in the

SCI Control Register (SCICR) determines the length of data characters.

10.6.4.2 Character Reception

During an SCI reception, the Receive Shift register shifts a frame in from the RXD pin. The data

is read from the SCI Data Register (SCIDR).

After a complete frame shifts into the Receive Shift register, the data portion of the frame

transfers to the SCI Data Register. The Receive Data Register Full (RDRF) flag in the SCI Status

Interrupt Enable (RFIE) bit in the SCI Control Register (SCICR) is also set, the RDRF flag

generates an RDRF interrupt request. If RDE is set, the RDRF interrupt is suppressed and a

Receive DMA request is generated instead.

WAKE

654

321

11-Bit Receive Shift Register

Data

Wake Up

Parity

Checking

SCI Data Register

RFIE

REIE

RWU

RDRF

INTERNAL BUS

RXD

Module

RERR Interrupt Request

RDRF/OR Interrupt Request

SBR12–SBR0

Baud Divider

LOOP

RSRC

From TXD Pin

or Transmitter

Clock

RERR

RAF

Recovery

CONTROL

Logic

POL

RDE

Receiver DMA Request

RIIE

RIDLE

Interrupt

Request

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