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DSP56857 bảng dữ liệu(PDF) 241 Page - Freescale Semiconductor, Inc |
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DSP56857 bảng dữ liệu(HTML) 241 Page - Freescale Semiconductor, Inc |
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241 / 662 page ![]() Module Memory Maps Serial Communications Interface (SCI), Rev. 4 Freescale Semiconductor 10-5 10.5 Module Memory Maps The five accessible registers on the SCI0 are listed in Table 10-2 while the five accessible registers on the SCI1 are listed in Table 10-3. Table 10-2. SCI0 Module Memory Map (SCI0_BASE = $1FFFE0) Address Offset Register Acronym Register Name Access Type Chapter Location Base + $0 SCI_0_BR SCI Baud Rate Register Read/Write Section 10.9.1 Base + $1 SCI_0_CR SCI Control Register Read/Write Section 10.9.2 Base + $2 SCI_0_CR2 SCI Control Register 2 Read/Write Section 10.9.3 Base + $3 SCI_0_SR SCI Status Register Read Only Section 10.9.4 Base + $4 SCI_0_DR SCI Data Register Read/Write Section 10.9.5 Table 10-3. SCI1 Module Memory Map (SCI1_BASE = $1FFDF8) Address Offset Register Acronym Register Name Access Type Chapter Location Base + $0 SCI_1_BR SCI Baud Rate Register Read/Write Section 10.9.1 Base + $1 SCI_1_CR SCI Control Register Read/Write Section 10.9.2 Base + $2 SCI_1_CR2 SCI Control Register 2 Read/Write Section 10.9.3 Base + $3 SCI_1_SR SCI Status Register Read Only Section 10.9.4 Base + $4 SCI_1_DR SCI Data Register Read/Write Section 10.9.5 Add. Offset Register Name 15 14 13 12 11 10 9876543 21 0 $0 SCIBR R 0 0 0 SBR W $1 SCICR R LOOP SWAI RSRC M WAKE POL PE PT TEIE TIIE RFIE REIE TE RE RWU SBK W $2 SCICR2 R 0 0 0 0 0 0 0 0 0 0 0 0 0 RIIE TDE RDE W $3 SCISR R TDRE TIDLE RDRF RIDLE OR NF FE PF 0 0 0 0 0 0 0 RAF W $4 SCIDR R 0 0 0 0 0 0 0 RECEIVE DATA W TRANSMIT DATA R 0 Read as 0 W Reserved Figure 10-2. SCI Register Map Summary |
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