DSP56857 datasheet(229/662 Pages) FREESCALE

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Direct Memory Access (DMA), Rev. 4

Freescale Semiconductor

9-11

restoration allows the circular queue to continuously update with new data without additional

Central Processing Unit (CPU) intervention.

Note:

If interrupts are enabled while in the Circular Queue mode the DMA Transfer Count

Note:

If both the source and destination registers are set to change using post- increment or

post-decrement, both registers will be returned to their initial values.

9.6.3 DMA Transfer Count (DMACNT)

Figure 9-5. DMA Transfer Count (DMACNT)

See Programmer’s Sheet on Appendix page B - 49

9.6.3.1 Transfer Count (DMACNT)—Bits 15–0

This is the count of the number of items (bytes or words) to transfer in the DMA data block. This

value is decremented after each DMA write operation. If DMA interrupts are enabled, a DMA

interrupt will be asserted when this count reaches zero. If circular queue operation is enabled, the

Transfer Count register is reloaded with its initial count value when it reaches zero. This permits

continuous DMA operation without additional Central Processing Unit (CPU) intervention. In

the circular queue operational mode and interrupts enabled an interrupt is issued each time the

transfer count reaches zero, if DMA. Each interrupt indicates the complete transfer of one

count-sized block of data.

9.6.4 DMA Destination Address Low (DMADAL)

Figure 9-6. DMA Destination Address Low (DMADAL)

See Programmer’s Sheet on Appendix page B - 48

9.6.4.1 Destination Address Low (DMADAL)—Bits 15–0

This is the lower word of the DMA Destination Address. DMA data is written from this address.

If post-incrementing (or decrementing) is enabled, this value is updated with each write

transaction.

Base + $2

Read

DMA TRANSFER COUNT

Write

Reset

000

Base+ $3

Read

DMA DESTINATION ADDRESS (LOW)

Write

Reset

000

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