DSP56857 datasheet(233/662 Pages) FREESCALE

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Programming Examples

Direct Memory Access (DMA), Rev. 4

Freescale Semiconductor

9-15

Note:

Because this scenario wishes to store the byte sized data in reverse order, the initial

destination address $2000 + $100 -1 = $20FF.

Note:

The Transfer Control Register is written to increment the Source Address Register and

decrement the Destination Address Register.

In step seven, the DMA is enabled (DAMON =1), DMA Interrupts are enabled (INTRON = 1),

the DMA Interrupt Pending bit is cleared, the DMA data size is set to byte, $0 is written to the

Peripheral Select field (indicating a memory-to-memory DMA operation), the DMA source is set

to increment by bytes (CSSIM = 0), and the DMA destination address is set to decrement by

bytes (DSIM = 11).

9.7.3 Peripheral-to-Memory Circular Queue DMA Operation

In this scenario, assume you want to transfer data from a SCI peripheral in a continuous transfer

mode. The SCI0 data read register is at $1FFFE4. The SCI0 is assigned to DMA_REQ[3],

illustrated in Table 9-10. The SCI is transferring one byte at a time, but it is stored as a word.

You want the DMA to interrupt the core at the completion of each 40-word packet. The data is to

be placed into a 400-word circular queue beginning at address $5000. Figure 9-11 illustrates this

operation.

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