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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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DSP56857 bảng dữ liệu(PDF) 227 Page - Freescale Semiconductor, Inc |
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DSP56857 bảng dữ liệu(HTML) 227 Page - Freescale Semiconductor, Inc |
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227 / 662 page  Register Descriptions (DMA_BASES = $1FFEC0, $1FFEC8, $1FFED0, $1FFED8, $1FFEE0, $1FFEE8) Direct Memory Access (DMA), Rev. 4 Freescale Semiconductor 9-9 9.6.1.5 Reserved—Bits 11–9 These bits are reserved or not implemented. They are read as, and written with 0s. 9.6.1.6 Peripheral Select (PERIPH_SEL)—Bits 8–4 This five-bit field selects one of 16 possible DMA peripherals. Table 9-10 illustrates the peripheral selected for each setting of this field. When the DMA is enabled, the peripheral chosen by this field controls the start of the DMA operation. That is, when the selected DMA_REQ [PERIPHERAL SELECT] line is asserted, the DMA operation begins. Note: If PERIPHERAL SELECT is equal to zero, DMA operation begins immediately after DMA operation is enabled (via asserting the DMA ON bit). This mechanism may be used for memory-to-memory transfers. If a peripheral-to-peripheral DMA transfer is desired, PERIPHERAL SELECT should be set to the slower of the two peripherals to prevent data overruns. Note: Whenever doing DMA transfers with peripherals, DATASIZE should be set as word mode. Table 9-10. DMA_REQ Connections DMA_REQ Line Peripheral Transfer Control Register Peripheral Select Field 15 HI8 High Transmitter 16 14 HI8 High Receiver 15 13 ESSI1 Transmitter 2 14 12 ESSI1 Transmitter 1 13 11 ESSI1 Transmitter 0 12 10 ESSI1 Receiver 11 9 ESSI0 Transmitter 2 10 8 ESSI0 Transmitter 1 9 7 ESSI0 Transmitter 0 8 6 ESSI0 Receiver 7 5 SCI1 Transmitter 6 4 SCI1 Receiver 5 3 SCI0 Transmitter 4 2 SCI0 Receiver 3 1 SPI Transmitter 2 0 SPI Receiver 1 |
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