DSP56857 datasheet(228/662 Pages) FREESCALE

228 / 662 page

5685X Digital Signal Controller User Manual, Rev. 4

9-10

Freescale Semiconductor

To select a peripheral to trigger a DMA operation, the peripheral select field of the DMA

Transfer Control Register is written with the value DMA_REQ line + 1. For example, if you want

the SCI1 Receiver to initiate a DMA request, write the value 5 into the peripheral select field of

the DMA Transfer Control Register.

9.6.1.7 Source Sign/Magnitude (SS/M)—Bits 3–2

This two-bit field determines how the DMA Source Address Register gets changed after each

DMA read operation. The Source Address Register may remain unchanged, be

post-incriminated, or be post-decremented as follows:

•

0x = Do not change the address register

•

10 = Increment the address register (by the DATA SIZE amount) after each read

•

11 = Decrement the address register (by the DATA SIZE amount) after each read

9.6.1.8 Destination Sign/Magnitude (DS/M)—Bits 1–0

This two-bit field determines how the DMA Destination Address Register gets changed after

each DMA write operation. The Destination Address Register may remain unchanged, be

post-incriminated, or be post-decremented as follows:

•

0x = Do not change the address register

•

10 = Increment the address register (by the DATA SIZE amount) after each read

•

11 = Decrement the address register (by the DATA SIZE amount) after each read

9.6.2 DMA Circular Queue Size (DMACQS)

Figure 9-4. DMA Circular Queue Size (DMACQS)

See Programmer’s Sheet on Appendix page B - 50

9.6.2.1 Circular Queue Size (DMACQS)—Bits 15–0

This register determines the size of the Circular Queue. It defaults to all zeros. When zero,

circular queue operation is disabled. When the Circular Queue Size is non-zero, circular queue

mode is operational. In this mode, the DMA Destination Address Register changes with

post-increments or post-decrements for each DMA write operation. The Circular Queue Size is

decremented after each write. When the Circular Queue Size reaches zero it is restored to its

initial value. The DMA Destination Address Register is also restored to its initial value. This

Base+ $1

Read

DMA CIRCULAR QUEUE SIZE

Write

Reset

000

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