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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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DSP56857 bảng dữ liệu(PDF) 223 Page - Freescale Semiconductor, Inc |
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DSP56857 bảng dữ liệu(HTML) 223 Page - Freescale Semiconductor, Inc |
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223 / 662 page  Module Memory Maps Direct Memory Access (DMA), Rev. 4 Freescale Semiconductor 9-5 9.4 Module Memory Maps The 5685x devices contain six independent DMA channels. Each DMA channel includes seven user-programmable 16-bit registers. Base addresses of each register set are provided in Table 9-4 through Table 9-9. Table 9-4. DMA 0 Register Address Map (DMA0_BASE = $1FFEC0) Address Offset Register Acronym Register Name Accesss Type Chapter Location Base + $0 DMA_3_TC Transfer Control Read/Write Section 9.6.1 Base + $1 DMA_3_CQS Circular Queue Size Read/Write Section 9.6.2 Base + $2 DMA_3_TC Transfer Count Read/Write Section 9.6.3 Base + $3 DMA_3_DAL Destination Address-Low Read/Write Section 9.6.4 Base + $4 DMA_3_DAH Destination Address-High Read/Write Section 9.6.5 Base + $5 DMA_3_SAL Source Address-Low Read/Write Section 9.6.6 Base + $6 DMA_3_SAH Source Address-High Read/Write Section 9.6.7 Table 9-5. DMA 1 Register Address Map (DMA1_BASE = $1FFEC8) Address Offset Register Acronym Register Name Accesss Type Chapter Location Base + $0 DMA_3_TC Transfer Control Read/Write Section 9.6.1 Base + $1 DMA_3_CQS Circular Queue Size Read/Write Section 9.6.2 Base + $2 DMA_3_TC Transfer Count Read/Write Section 9.6.3 Base + $3 DMA_3_DAL Destination Address-Low Read/Write Section 9.6.4 Base + $4 DMA_3_DAH Destination Address-High Read/Write Section 9.6.5 Base + $5 DMA_3_SAL Source Address-Low Read/Write Section 9.6.6 Base + $6 DMA_3_SAH Source Address-High Read/Write Section 9.6.7 Table 9-6. DMA 2 Register Address Map (DMA2_BASE = $1FFED0) Address Offset Register Acronym Register Name Access Type Chapter Location Base + $0 DMA_3_TC Transfer Control Read/Write Section 9.6.1 Base + $1 DMA_3_CQS Circular Queue Size Read/Write Section 9.6.2 Base + $2 DMA_3_TC Transfer Count Read/Write Section 9.6.3 Base + $3 DMA_3_DAL Destination Address-Low Read/Write Section 9.6.4 Base + $4 DMA_3_DAH Destination Address-High Read/Write Section 9.6.5 Base + $5 DMA_3_SAL Source Address-Low Read/Write Section 9.6.6 Base + $6 DMA_3_SAH Source Address-High Read/Write Section 9.6.7 |
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