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IMX7SCEC bảng dữ liệu(PDF) 99 Page - NXP Semiconductors

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Giải thích chi tiết về linh kiện  i.MX 7Solo Family
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IMX7SCEC bảng dữ liệu(HTML) 99 Page - NXP Semiconductors

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Electrical characteristics
i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017
NXP Semiconductors
99
4.10.8.9
Low-power receiver timing
Input Glitch Rejection of Low-Power Receivers
4.10.9
Pulse width modulator (PWM) timing parameters
This section describes the electrical information of the PWM. The PWM can be programmed to select one
of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before
being input to the counter. The output is available at the pulse-width modulator output (PWMO) external
pin.
Figure 70 depicts the timing of the PWM, and Table 71 lists the PWM timing parameters.
Figure 70. PWM Timing
4.10.10 QUAD SPI (QSPI) Timing Parameters
Measurement conditions are with 35 pF load on SCK and SIO pins and input slew rate of 1 V/ns.
Table 71. PWM output timing parameters
ID
Parameter
Min
Max
Unit
PWM Module Clock Frequency
0
ipg_clk
MHz
P1
PWM output pulse width high
15
ns
P2
PWM output pulse width low
15
ns
2*TLPX
2*TLPX
TMIN-RX
TMIN-RX
eSPIKE
eSPIKE
Input
Output
VIH
VIL



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