IMX7SCEC datasheet(83/152 Pages) NXP

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Electrical characteristics

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

4.10.2.6

Bus operation condition for 3.3 V and 1.8 V signaling

Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50

mode is 1.8 V. The DC parameters for the NVCC_SD1, NVCC_SD2 and NVCC_SD3 supplies are

identical to those shown in Table 22, "GPIO DC Parameters," on page 38.

4.10.3

Ethernet controller (ENET) AC electrical specifications

The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive

at timing specs/constraints for the physical interface.

4.10.3.1

ENET MII mode timing

This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal

timings.

4.10.3.1.1

MII receive signal timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN,

ENET_RX_ER, and ENET_RX_CLK)

The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1%. There

is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the

ENET_RX_CLK frequency.

Figure 51 shows MII receive signal timings. Table 59 describes the timing parameters (M1–M4) shown in

the figure.

Figure 51. MII receive signal timing diagram

ENET_RX_CLK (input)

ENET_RX_DATA3,2,1,0

ENET_RX_ER

ENET_RX_EN

(inputs)

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