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IMX7SCEC bảng dữ liệu(PDF) 27 Page - NXP Semiconductors

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Giải thích chi tiết về linh kiện  i.MX 7Solo Family
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IMX7SCEC bảng dữ liệu(HTML) 27 Page - NXP Semiconductors

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Electrical characteristics
i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017
NXP Semiconductors
27
4.1.6
Power modes
The i.MX 7Solo has the following power modes:
•
OFF mode: all power rails are off
•
SNVS mode: only RTC and tamper detection logic is active
•
LPSR mode: an extension of SNVS mode, with 16 GPIOs in low power state retention mode
•
RUN Mode: all external power rails are on, CPU is active and running, other internal module can
be on/off based on application;
•
Low Power mode (System Idle, Low Power Idle, and Deep Sleep): most external power rails are
still on, CPU is in WFI state or power gated, most of the internal modules are clock gated or power
gated
The valid power mode transition is shown in this diagram.
Figure 3. i.MX 7Solo Power Modes
The power mode transition condition is defined in the following table.
Table 13. Power Mode Transition
Transition
From
To
Condition
1
OFF
RUN
VDD_SVNS_IN supply present.
2
SNVS
OFF
VDD_SNVS_IN supply removal.
3
RUN
SNVS
ONOFF long press, or SW.
4
SNVS
RUN
ONOFF press, or RTC, or tamper event.
5
RUN
LPSR
SW.
6
LPSR
RUN
ONOFF press, or RTC, or tamper event, or GPIO event.
7
RUN
Low Power SW (CPU execute WFI)
8
Low Power
RUN
RTC, tamper event, IRQ.
OFF
RUN
SNVS
LPSR
Low
Power
1
2
3
4
5
6
7
8



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