IMX7SCEC datasheet(54/152 Pages) NXP

54 / 152 page

Electrical characteristics

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

Figure 17. 16-Bit Muxed A/D Mode, Synchronous Read Access, WSC=7, RADVN=1, ADH=1, OEA=0

4.8.3.4

General EIM timing—Asynchronous mode

Figure 18 through Figure 22, and Table 39 help you determine timing parameters relative to the chip

select (CS) state for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the

timing parameters mentioned above.

Asynchronous read & write access length in cycles may vary from what is shown in Figure 18 through

Figure 21 as RWSC, OEN and CSN is configured differently. See the i.MX 7Solo Application Processor

Reference Manual (IMX7SRM) for the EIM programming model.

Figure 18. Asynchronous memory read access (RWSC = 5)

Last

EIM_BCLK

EIM_ADDRxx/

EIM_WE_B

EIM_LBA_B

EIM_OE_B

EIM_EBx_B

EIM_CSx_B

Address V1

Data

Valid Address

EIM_ADxx

WE5

WE6

WE7

WE14

WE15

WE10

WE11

WE12

WE13

WE18

WE19

WE4

Last Valid Address

Address V1

D(V1)

EIM_ADDRxx/

EIM_DATAxx[7:0]

EIM_WE_B

EIM_LBA_B

EIM_OE_B

EIM_EBx_B

EIM_CSx_B

Next Address

WE39

WE35

WE37

WE32

WE36

WE38

WE43

WE40

WE31

WE44

INT_CLK

start of

access

end of

access

MAXDI

MAXCSO

MAXCO

EIM_ADxx

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