IMX7SCEC datasheet(5/152 Pages) NXP

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i.MX 7Solo introduction

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

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Frequency of the core (including NEON and L1 cache), as per Table 9.

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NEON MPE coprocessor

— SIMD Media Processing Architecture

— NEON register file with 32x64-bit general-purpose registers

— NEON Integer execute pipeline (ALU, Shift, MAC)

— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)

— NEON load/store and permute pipeline

The ARM Cortex-M4 platform:

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Cortex-M4 CPU core

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MPU (memory protection unit)

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FPU (floating-point unit)

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16 KByte instruction cache

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16 KByte data cache

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64 KByte TCM (tightly-coupled memory)

The SoC-level memory system consists of the following additional components:

— Boot ROM, including HAB (96 KB)

— Internal multimedia / shared, fast access RAM (256 KB of total OCRAM)

— Secure/nonsecure RAM (32 KB)

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External memory interfaces: The i.MX 7Solo family of processors supports the latest,

high-volume, cost effective DRAM, NOR, and NAND Flash memory standards.

— Up to 32-bit LP-DDR2-1066, DDR3-1066, DDR3L-1066, and LPDDR3-1066

— 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,

BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 62 bits.

— 16/32-bit NOR Flash. All EIMv2 pins are muxed on other interfaces.

Each i.MX 7Solo processor enables the following interfaces to external devices (some of them are muxed

and not available simultaneously):

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Displays—Available interfaces.

— One parallel 24-bit display port

— One MIPI DSI port

•

Camera sensors:

— One parallel Camera port (up to 24 bit and up to 133 MHz peak)

— One MIPI-CSI port

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Expansion cards:

— Three MMC/SD/SDIO card ports all supporting the following. Moreover, the third port can

support HS400.

– 1-bit or 4-bit transfer mode specifications for SD and SDIO cards, up to 208 MHz

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