IMX7SCEC datasheet(80/152 Pages) NXP

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Electrical characteristics

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

4.10.2.3

HS400 AC timing—eMMC5.0 only

Figure 48 depicts the timing of HS400. Table 56 lists the HS400 timing characteristics. Be aware that only

data is sampled on both edges of the clock (not applicable to CMD). The CMD input/output timing for

HS400 mode is the same as CMD input/output timing for SDR104 mode. Check SD5, SD6 and SD7

parameters in Table 58 SDR50/SDR104 Interface Timing Specification for CMD input/output timing for

HS400 mode.

Figure 48. HS400 timing

SD3

uSDHC Input Setup Time

tISU

2.4

—

SD4

uSDHC Input Hold Time

tIH

1.3

—

Table 56. HS400 interface timing specifications

Parameter

Symbols

Min

Max

Unit

Card Input clock

SD1

Clock Frequency

fPP

200

Mhz

SD2

Clock Low Time

tCL

0.46

× tCLK

0.54

× tCLK

SD3

Clock High Time

tCH

0.46

× tCLK

0.54

× tCLK

uSDHC Output/Card inputs DAT (Reference to SCK)

SD4

Output Skew from Data of

Edge of SCK

tOSkew1

0.45

—

SD5

Output Skew from Edge of

SCK to Data

tOSkew2

0.45

—

Table 55. eMMC4.4/4.41 interface timing specification(continued)

Parameter

Symbols

Min

Max

Unit

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