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MSP432P411VIPZ bảng dữ liệu(PDF) 111 Page - Texas Instruments |
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MSP432P411VIPZ bảng dữ liệu(HTML) 111 Page - Texas Instruments |
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111 / 212 page  111 MSP432P4111, MSP432P4011, MSP432P411Y MSP432P401Y, MSP432P411V, MSP432P401V www.ti.com SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018 Submit Documentation Feedback Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V Detailed Description Copyright © 2017–2018, Texas Instruments Incorporated Table 6-22. PMAP Registers (Base Address: 0x4000_5000) (continued) REGISTER NAME ACRONYM OFFSET Port Mapping P3.3 P3MAP3 1Bh Port Mapping P3.4 P3MAP4 1Ch Port Mapping P3.5 P3MAP5 1Dh Port Mapping P3.6 P3MAP6 1Eh Port Mapping P3.7 P3MAP7 1Fh Port Mapping P7.0 P7MAP0 38h Port Mapping P7.1 P7MAP1 39h Port Mapping P7.2 P7MAP2 3Ah Port Mapping P7.3 P7MAP3 3Bh Port Mapping P7.4 P7MAP4 3Ch Port Mapping P7.5 P7MAP5 3Dh Port Mapping P7.6 P7MAP6 3Eh Port Mapping P7.7 P7MAP7 3Fh Table 6-23. Capacitive Touch I/O 0 Registers (Base Address: 0x4000_5400) REGISTER NAME ACRONYM OFFSET Capacitive Touch I/O 0 Control CAPTIO0CTL 0Eh Table 6-24. Capacitive Touch I/O 1 Registers (Base Address: 0x4000_5800) REGISTER NAME ACRONYM OFFSET Capacitive Touch I/O 1 Control CAPTIO1CTL 0Eh Table 6-25. Timer32 Registers (Base Address: 0x4000_C000) REGISTER NAME ACRONYM OFFSET Timer 1 Load T32LOAD1 00h Timer 1 Current Value T32VALUE1 04h Timer 1 Timer Control T32CONTROL1 08h Timer 1 Interrupt Clear T32INTCLR1 0Ch Timer 1 Raw Interrupt Status T32RIS1 10h Timer 1 Interrupt Status T32MIS1 14h Timer 1 Background Load T32BGLOAD1 18h Timer 2 Load T32LOAD2 20h Timer 2 Current Value T32VALUE2 24h Timer 2 Timer Control T32CONTROL2 28h Timer 2 Interrupt Clear T32INTCLR2 2Ch Timer 2 Raw Interrupt Status T32RIS2 30h Timer 2 Interrupt Status T32MIS2 34h Timer 2 Background Load T32BGLOAD2 38h Table 6-26. DMA Registers (Base Address: 0x4000_E000) REGISTER NAME ACRONYM OFFSET Device Configuration Status DMA_DEVICE_CFG 000h Software Channel Trigger DMA_SW_CHTRIG 004h Channel 0 Source Configuration DMA_CH0_SRCCFG 010h Channel 1 Source Configuration DMA_CH1_SRCCFG 014h Channel 2 Source Configuration DMA_CH2_SRCCFG 018h |
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