MSP432P411VIPZ datasheet(198/212 Pages) TI1

198 / 212 page

Using an external

positive reference

Connection to onboard ground

VeREF-

VREF+/VeREF+

50 nF

5 F

AVSS

198

MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Applications, Implementation, and Layout

See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal

oscillator with the MSP432 devices.

7.1.3

General Layout Recommendations

•

Use proper grounding and short traces for the external crystal to reduce parasitic capacitance. See

MSP430 32-kHz Crystal Oscillators for recommended layout guidelines.

•

Use specified bypass capacitors on DVCC, AVCC, and reference pins, if used.

•

Do not route any high-frequency signal close to an analog signal line. For example, keep digital

switching signals such as PWM or JTAG signals away from the oscillator circuit.

•

Design in proper ESD level protection to protect the device from unintended high-voltage electrostatic

discharge. See MSP430 System-Level ESD Considerations for guidelines.

7.1.4

Do's and Don'ts

TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up,

power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the

limits specified in Section 5.1. Exceeding the specified limits may cause malfunction of the device.

7.2

Peripheral and Interface-Specific Design Information

7.2.1

Precision ADC Peripheral

7.2.1.1

Partial Schematic

Figure 7-3 shows the recommended circuit for grounding and noise reduction.

Figure 7-3. Precision ADC Grounding and Noise Considerations

7.2.1.2

Design Requirements

As with any high-resolution ADC, follow appropriate PCB layout and grounding techniques to eliminate

ground loops, unwanted parasitic effects, and noise.

Ground loops are formed when return current from the ADC flows through paths that are common with

other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset

voltages that can add to or subtract from the reference or input voltages of the ADC. The general

guidelines in Section 7.1.1 combined with the connections shown in Section 7.2.1.1 prevent this.

In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital

switching or switching power supplies can corrupt the conversion result. TI recommends a noise-free

design using separate analog and digital ground planes with a single-point connection to achieve high

accuracy.

Figure 7-3 shows the recommended decoupling circuit when an external voltage reference is used.

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