MSP432P411VIPZ datasheet(189/212 Pages) TI1

189 / 212 page

189

MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

www.ti.com

SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Detailed Description

(1)

X = Don't care

(2)

Setting PJSEL1.3 = 0 and PJSEL0.3 = 1 causes the general-purpose I/O to be disabled. When HFXTBYPASS = 0, PJ.2 and PJ.3 are

configured for crystal operation and PJSEL1.2 and PJSEL0.2 are don't care. When HFXTBYPASS = 1, PJ.3 is configured for bypass

operation and PJ.2 is configured as general-purpose I/O.

(3)

When PJ.3 is configured in bypass mode, PJ.2 is configured as general-purpose I/O.

(4)

With PJSEL0.2 = 1 or PJSEL1.2 = 1 the general-purpose I/O functionality is disabled. No input function is available. When configured as

output, the pin is actively pulled to zero.

Table 6-85. Port PJ (PJ.2 and PJ.3) Pin Functions

PIN NAME (PJ.x)

FUNCTION

CONTROL BITS OR SIGNALS (1)

PJDIR.x

PJSEL1.2

PJSEL0.2

PJSEL1.3

PJSEL0.3

HFXT

BYPASS

PJ.3/HFXIN

PJ.3 (I/O)

I: 0; O: 1

N/A

DVSS

HFXIN crystal mode (2)

HFXIN bypass mode (2)

PJ.2/HFXOUT

PJ.2 (I/O)

I: 0; O: 1

1 (3)

N/A

See (4)

1 (3)

DVSS

See (4)

1 (3)

HFXOUT crystal mode (2)

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