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MSP432P411VIPZ bảng dữ liệu(PDF) 186 Page - Texas Instruments

tên linh kiện MSP432P411VIPZ
Giải thích chi tiết về linh kiện  SimpleLink Mixed-Signal Microcontrollers
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MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
www.ti.com
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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V
Detailed Description
Copyright © 2017–2018, Texas Instruments Incorporated
(1)
X = Don't care
(2)
Setting PJSEL1.0 = 0 and PJSEL0.0 = 1 causes the general-purpose I/O to be disabled. When LFXTBYPASS = 0, PJ.0 and PJ.1 are
configured for crystal operation and PJSEL1.1 and PJSEL0.1 are don't care. When LFXTBYPASS = 1, PJ.0 is configured for bypass
operation and PJ.1 is configured as general-purpose I/O.
(3)
When PJ.0 is configured in bypass mode, PJ.1 is configured as general-purpose I/O.
(4)
With PJSEL0.1 = 1 or PJSEL1.1 = 1 the general-purpose I/O functionality is disabled. No input function is available. When configured as
output, the pin is actively pulled to zero.
Table 6-84. Port PJ (PJ.0 and PJ.1) Pin Functions
PIN NAME (PJ.x)
x
FUNCTION
CONTROL BITS OR SIGNALS (1)
PJDIR.x
PJSEL1.1
PJSEL0.1
PJSEL1.0
PJSEL0.0
LFXT
BYPASS
PJ.0/LFXIN
0
PJ.0 (I/O)
I: 0; O: 1
X
X
0
0
X
N/A
0
X
X
1
X
X
DVSS
1
LFXIN crystal mode (2)
X
X
X
0
1
0
LFXIN bypass mode (2)
X
X
X
0
1
1
PJ.1/LFXOUT
1
PJ.1 (I/O)
I: 0; O: 1
0
0
0
0
0
1
X
X
X
1 (3)
N/A
0
See (4)
See (4)
0
0
0
1
X
X
X
1 (3)
DVSS
1
See (4)
See (4)
0
0
0
1
X
X
X
1 (3)
LFXOUT crystal mode (2)
X
X
X
0
1
0



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