MSP432P411VIPZ datasheet(181/212 Pages) TI1

181 / 212 page

181

MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Detailed Description

(1)

X = Don't care

(2)

Not available on the 64-pin RGC package.

(3)

Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog

signals are applied.

(4)

Setting P10SEL1.x and P10SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

(5)

Setting the CEPD.q bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents

when applying analog signals. Selecting the C0.q input pin to the comparator multiplexer with the CEIPSEL or CEIMSEL bits

automatically disables the output driver and input buffer for that pin, regardless of the state of the associated CEPD.q bit.

Table 6-82. Port P10 (P10.4 and P10.5) Pin Functions

PIN NAME (P10.x)

FUNCTION

CONTROL BITS OR SIGNALS (1)

P10DIR.x

P10SEL1.x

P10SEL0.x

P10.4/TA3.0/C0.7/L35 (2)

P10.4 (I/O)

I: 0; O: 1

TA3.CCI0A

TA3.0

L35 (3)

C0.7 (4) (5)

P10.5/TA3.1/C0.6/L34 (2)

P10.5 (I/O)

I: 0; O: 1

TA3.CCI1A

TA3.1

L34 (3)

C0.6 (4) (5)

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