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MSP432P411VIPZ bảng dữ liệu(PDF) 175 Page - Texas Instruments

tên linh kiện MSP432P411VIPZ
Giải thích chi tiết về linh kiện  SimpleLink Mixed-Signal Microcontrollers
PDF  212 Pages
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Trang chủ  http://www.ti.com
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MSP432P411VIPZ bảng dữ liệu(HTML) 175 Page - Texas Instruments

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MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
www.ti.com
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Submit Documentation Feedback
Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V
Detailed Description
Copyright © 2017–2018, Texas Instruments Incorporated
(1)
X = Don't care
(2)
Not available on the 64-pin RGC package.
(3)
Direction controlled by eUSCI_B1 module.
(4)
Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog
signals are applied.
(5)
Setting P6SEL1.x and P6SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(6)
Setting the CEPD.q bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the C1.q input pin to the comparator multiplexer with the CEIPSEL or CEIMSEL bits
automatically disables the output driver and input buffer for that pin, regardless of the state of the associated CEPD.q bit.
Table 6-79. Port P6 (P6.2 to P6.5) Pin Functions
PIN NAME (P6.x)
x
FUNCTION
CONTROL BITS OR SIGNALS (1)
P6DIR.x
P6SEL1.x
P6SEL0.x
P6.2/UCB1STE/C1.5/L27 (2)
2
P6.2 (I/O)
I: 0; O: 1
0
0
UCB1STE
X (3)
0
1
L27 (4)
X
1
0
C1.5 (5) (6)
X
1
1
P6.3/UCB1CLK/C1.4/L26 (2)
3
P6.3 (I/O)
I: 0; O: 1
0
0
UCB1CLK
X (3)
0
1
L26 (4)
X
1
0
C1.4 (5) (6)
X
1
1
P6.4/UCB1SIMO/UCB1SDA/C1
.3/L25 (2)
4
P6.4 (I/O)
I: 0; O: 1
0
0
UCB1SIMO/UCB1SDA
X (3)
0
1
L25 (4)
X
1
0
C1.3 (5) (6)
X
1
1
P6.5/UCB1SOMI/UCB1SCL/C1.
2/L24 (2)
5
P6.5 (I/O)
I: 0; O: 1
0
0
UCB1SOMI/UCB1SCL
X (3)
0
1
L24 (4)
X
1
0
C1.2 (5) (6)
X
1
1



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