MC68HC908AP16CFB datasheet(133/440 Pages) MOTOROLA

133 / 440 page

System Integration Module (SIM)

Reset and System Initialization

MC68HC908AP Family — Rev. 2.5

Data Sheet

MOTOROLA

133

9.2.3 Clocks in Stop Mode and Wait Mode

Upon exit from stop mode by an interrupt, break, or reset, the SIM allows

ICLK to clock the SIM counter. The CPU and peripheral clocks do not

become active until after the stop delay timeout. This timeout is

selectable as 4096 or 32 ICLK cycles. (See 9.6.2 Stop Mode.)

In wait mode, the CPU clocks are inactive. The SIM also produces two

sets of clocks for other modules. Refer to the wait mode subsection of

each module to see if the module is active or inactive in wait mode.

Some modules can be programmed to be active in wait mode.

9.3 Reset and System Initialization

The MCU has these reset sources:

•

Power-on reset module (POR)

•

External reset pin (RST)

•

Computer operating properly module (COP)

•

Low-voltage inhibit module (LVI)

•

Illegal opcode

•

Illegal address

All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in

monitor mode) and assert the internal reset signal (IRST). IRST causes

all registers to be returned to their default values and all modules to be

returned to their reset states.

An internal reset clears the SIM counter (see 9.4 SIM Counter), but an

external reset does not. Each of the resets sets a corresponding bit in

the SIM reset status register (SRSR). (See 9.7 SIM Registers.)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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