MC68HC908AP16CFB datasheet(135/440 Pages) MOTOROLA

135 / 440 page

System Integration Module (SIM)

Reset and System Initialization

MC68HC908AP Family — Rev. 2.5

Data Sheet

MOTOROLA

135

Figure 9-5. Internal Reset Timing

The COP reset is asynchronous to the bus clock.

Figure 9-6. Sources of Internal Reset

The active reset feature allows the part to issue a reset to peripherals

and other chips within a system built around the MCU.

9.3.2.1 Power-On Reset

When power is first applied to the MCU, the power-on reset module

(POR) generates a pulse to indicate that power-on has occurred. The

external reset pin (RST) is held low while the SIM counter counts out

4096 + 32 ICLK cycles. Thirty-two ICLK cycles later, the CPU and

memories are released from reset to allow the reset vector sequence to

occur.

At power-on, these events occur:

•

A POR pulse is generated.

•

The internal reset signal is asserted.

•

The SIM enables CGMOUT.

•

Internal clocks to the CPU and modules are held inactive for 4096

ICLK cycles to allow stabilization of the oscillator.

•

The pin is driven low during the oscillator stabilization time.

•

The POR bit of the SIM reset status register (SRSR) is set and all

other bits in the register are cleared.

IRST

RST

RST PULLED LOW BY MCU

IAB

32 CYCLES

VECTOR HIGH

ICLK

ILLEGAL ADDRESS RST

ILLEGAL OPCODE RST

COPRST

LVI

POR

INTERNAL RESET

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC68HC908AP16CFB bảng dữ liệu(PDF) 135 Page - Motorola, Inc

MC68HC908AP16CFB bảng dữ liệu(HTML) 135 Page - Motorola, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL