TNETV2501INPGF datasheet(130/197 Pages) TI1

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Functional Overview

130

December 2002 − Revised November 2008

SPRS206K

3.16.1

IFR and IER Registers

The Interrupt Enable Registers (IER0 and IER1) control which interrupts will be masked or enabled during

normal operation. The Interrupt Flag Registers (IFR0 and IFR1) contain flags that indicate interrupts that are

currently pending.

The Debug Interrupt Enable Registers (DBIER0 and DBIER1) are used only when the CPU is halted in the

real-time emulation mode. If the CPU is running in real-time mode, the standard interrupt processing (IER0/1)

is used and DBIER0/1 are ignored.

A maskable interrupt enabled in DBIER0/1 is defined as a time-critical interrupt. When the CPU is halted in

the real-time mode, the only interrupts that are serviced are time-critical interrupts that are also enabled in an

interrupt enable register (IER0 or IER1).

Write the DBIER0/1 to enable or disable time-critical interrupts. To enable an interrupt, set its corresponding

bit. To disable an interrupt, clear its corresponding bit. Initialize these registers before using the real-time

emulation mode.

A DSP hardware reset clears IFR0/1, IER0/1, and DBIER0/1 to 0. A software reset instruction clears IFR0/1

to 0 but does not affect IER0/1 and DBIER0/1.

The bit layouts of these registers for each interrupt are shown in Figure 3−51 and Figure 3−52. For more

information on the IER, IFR, and DBIER registers, refer to the TMS320C55x DSP CPU Reference Guide

(literature number SPRU371).

DMAC5

DMAC4

Reserved

UART

INT3/

WDTINT‡

DSPINT

DMAC1

Reserved

R/W, 0

R/W, 0†

R/W, 0

XINT1

RINT1

RINT0

TINT0

INT2

INT0

Reserved

R/W, 0

R, 0

LEGEND: R = Read, W = Write, n = value at reset

† This bit must be kept zero when writing to IER0.

‡ WDTINT is generated only when the WDT interrupt pin is connected to INT3 through the TSSR.

Figure 3−51. IFR0, IER0, DBIFR0, and DBIER0 Registers Layout

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