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TNETV2501INPGF bảng dữ liệu(PDF) 126 Page - Texas Instruments |
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TNETV2501INPGF bảng dữ liệu(HTML) 126 Page - Texas Instruments |
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126 / 197 page  Functional Overview 126 December 2002 − Revised November 2008 SPRS206K Table 3−67. Device Revision ID WORD ADDRESS REGISTER NAME DESCRIPTION RESET VALUE† 0x3800 − 0x3803 Die ID Die ID 0x3804 Chip ID (LSW) Defines F# 3LS digits and PG rev 1001 0100 0110 xxxx 0x3805 Chip ID (MSW) Defines F# 3MS digits 0000 0111 0101 0001 0x3806 Sub ID Defines subsytem ID 0000 0000 0000 0000‡ † x denotes a “don’t care.” ‡ Denotes single core Table 3−68. I2C WORD ADDRESS REGISTER NAME DESCRIPTION RESET VALUE† 0x3C00 I2COAR§ I2C Own Address Register 0000 0000 0000 0000 0x3C01 I2CIER I2C Interrupt Enable Register 0000 0000 0000 0000 0x3C02 I2CSTR I2C Status Register 0000 0100 0001 0000 0x3C03 I2CCLKL I2C Clock Low-Time Divider Register 0000 0000 0000 0000 0x3C04 I2CCLKH I2C Clock High-Time Divider Register 0000 0000 0000 0000 0x3C05 I2CCNT I2C Data Count 0000 0000 0000 0000 0x3C06 I2CDRR I2C Data Receive Register 0000 0000 0000 0000 0x3C07 I2CSAR I2C Slave Address Register 0000 0011 1111 1111 0x3C08 I2CDXR I2C Data Transmit Register 0000 0000 0000 0000 0x3C09 I2CMDR I2C Mode Register 0000 0000 0000 0000 0x3C0A I2CISRC I2C Interrupt Source Register 0000 0000 0000 0000 0x3C0B I2CGPIO I2C General-Purpose Register (Not supported) xxxx xxxx xxxx xxxx 0x3C0C I2CPSC I2C Prescaler Register 0000 0000 0000 0000 0x3C0D PID1 I2C Peripheral ID Register 1 − 0x3C0E PID2 I2C Peripheral ID Register 2 − − I2CXSR I2C Transmit Shift Register − − I2CRSR I2C Receive Shift Register − † x denotes a “don’t care.” § Specifies a unique 5501 I2C address. This register is fully programmable in both 7-bit and 10-bit modes and must be set by the programmer. When this device is used in conjunction with another I2C device, it must be programmed to the I2C slave address (01011A2A1A0) allocated by Philips Semiconductor for the 5501 (allocation number: 1946). A2, A1, and A0 are programmable address bits. |
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