TNETV2501INPGF datasheet(109/197 Pages) TI1

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Functional Overview

109

December 2002 − Revised November 2008

SPRS206K

3.13.2

DPORT Interface

The DPORT interfaces the CPU to the EMIF module. The DPORT is capable of enabling write posting on the

EMIF module. Write posting prevents stalls to the CPU during external memory writes. Two write posting

registers, which are freely associated with E and F bus writes, exist within the DPORT and are used to store

the write address and data so that writes can be zero wait state for the CPU. External memory writes will not

generate stalls to the CPU unless the two write posting registers are filled. Write posting is enabled by setting

the WPE bit of the DCR to 1.

The EMIFTO bit of the DERR is used to indicate that a CPU, DMA, HPI, or IPORT access to external memory

has generated a time-out error. The time-out error feature is enabled through the EMIFTOEN bit of the

Time-Out Control Register (TOCR). This function is not recommended during normal operation of the 5501.

The DPORT can be placed into idle through the EMIFI bit of the Idle Control Register (ICR) and executing the

IDLE instruction. When the DPORT is in idle, it will stop accepting new EMIF requests. If there is a request

from the CPU or the EMIF, the DPORT will not respond and hang. The ICR register will generate a bus error

if the DPORT is idled without the CPU or Master Port domains being in idle.

3.13.2.1 DPORT Configuration Register (DCR)

The DPORT Configuration Register bit layout is shown in Figure 3−46 and the bits are described in

Table 3−50.

Reserved

R, 00000000

WPE

Reserved

R/W, 0

R, 0000000

LEGEND: R = Read, W = Write, n = value at reset

Figure 3−46. DPORT Configuration Register Layout (0x0200)

Table 3−50. DPORT Configuration Register Bit Field Description†

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

Reserved

15−8

00000000

Reserved

WPE

R/W

Write Posting Enable bit†

WPE = 0:

Write posting disabled

WPE = 1:

Write posting enabled

Reserved

6−0

0000000

Reserved

† Write posting should not be enabled or disabled while the EMIF is conducting a transaction with external memory.

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