TNETV2501INPGF datasheet(108/197 Pages) TI1

108 / 197 page

Functional Overview

108

December 2002 − Revised November 2008

SPRS206K

3.13.1.2 XPORT Bus Error Register (XERR)

The XPORT Bus Error Register bit layout is shown in Figure 3−45 and the bits are described in Table 3−49.

INTERR

Reserved

PERITO

Reserved

R, 0

R, 00

R, 0

R, 0000

Reserved

EBUS

DBUS

Reserved

R, 000

R, 0

R, 000

LEGEND: R = Read, W = Write, n = value at reset

Figure 3−45. XPORT Bus Error Register Layout (0x0102)

Table 3−49. XPORT Bus Error Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

INTERR

INTERR bit

INTERR = 0:

No error

INTERR = 1:

An error occurred during an access to one of the

registers listed in Table 3−47.

Reserved

14−13

Reserved

PERITO

PERITO bit

PERITO = 0:

No error

PERITO = 1:

A time-out error occurred during an access to a

peripheral register.

Reserved

11−5

0000000

Reserved

EBUS

EBUS error bit†

EBUS = 0:

No error

EBUS = 1:

An error occurred during an EBUS access (write) to

one of the registers listed in Table 3−47.

DBUS

DBUS error bit†

DBUS = 0:

No error

DBUS = 1:

An error occurred during a DBUS access (read) to

one of the registers listed in Table 3−47.

Reserved

2−0

000

Reserved

† See the TMS320C55x DSP CPU Reference Guide (literature number SPRU371) for more information on the D-bus and E-bus.

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