TNETV2501INPGF datasheet(178/197 Pages) TI1

178 / 197 page

Electrical Specifications

178

December 2002 − Revised November 2008

SPRS206K

Table 5−41. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)†‡§

NO.

MASTER

SLAVE

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

M58

tsu(DRV–CKXL)

Setup time, DR valid before CLKX low

0 − 5P

M59

th(CKXL–DRV)

Hold time, DR valid after CLKX low

9 + 6P

M60

tsu(FXL–CKXL)

Setup time, FSX low before CLKX low

M61

tc(CKX)

Cycle time, CLKX

16P

† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

‡ P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU

clock frequency, use P = 2/300 MHz = 6.66 ns.

§ McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the

TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592).

Table 5−42. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)†‡§¶

NO.

PARAMETER

MASTER

SLAVE

UNIT

NO.

PARAMETER

MIN

MAX

MIN

MAX

UNIT

M53

td(CKXH–FXL)

Delay time, CLKX high to FSX low#

D − 2

D + 6

M54

td(FXL–CKXL)

Delay time, FSX low to CLKX low||

T − 6

T + 4

M55

td(CKXH–DXV)

Delay time, CLKX high to DX valid

−4

M56

tdis(CKXH–DXHZ)

Disable time, DX high impedance following last data bit

from CLKX high

−2

3P + 4

4P + 18

M57

td(FXL–DXV)

Delay time, FSX low to DX valid

C − 2

C +10

2P − 4

4P + 10

† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

‡ P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU

clock frequency, use P = 2/300 MHz = 6.66 ns.

§ McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the

TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592).

¶ T = CLKX period = (1 + CLKGDV) * P

C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even

D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even

# FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

|| FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).

LSB

M61

M55

M58

M59

MSB

CLKX

FSX

Bit (n−1)

(n−2)

(n−3)

(n−4)

Bit 0

Bit (n−1)

(n−2)

(n−3)

(n−4)

M53

M56

M60

M54

M57

Figure 5−38. McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

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