TNETV2501INPGF datasheet(173/197 Pages) TI1

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Electrical Specifications

173

December 2002 − Revised November 2008

SPRS206K

5.15.3

McBSP as SPI Master or Slave Timings

Table 5−35 to Table 5−42 assume testing over recommended operating conditions (see Figure 5−35 through

Figure 5−38).

Table 5−35. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)†‡§

NO.

MASTER

SLAVE

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

M30

tsu(DRV–CKXL)

Setup time, DR valid before CLKX low

0 − 5P

M31

th(CKXL–DRV)

Hold time, DR valid after CLKX low

9 + 6P

M32

tsu(FXL–CKXH)

Setup time, FSX low before CLKX high

M33

tc(CKX)

Cycle time, CLKX

16P

† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

‡ P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU

clock frequency, use P = 2/300 MHz = 6.66 ns.

§ McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the

TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592).

Table 5−36. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)†‡§¶

NO.

PARAMETER

MASTER

SLAVE

UNIT

NO.

PARAMETER

MIN

MAX

MIN

MAX

UNIT

M24

td(CKXL–FXL)

Delay time, CLKX low to FSX low#

T − 2

T + 6

M25

td(FXL–CKXH)

Delay time, FSX low to CLKX high||

C − 6

C + 4

M26

td(CKXH–DXV)

Delay time, CLKX high to DX valid

−4

M27

tdis(CKXL–DXHZ)

Disable time, DX high impedance following last data bit from

CLKX low

C − 2

C +10

M28

tdis(FXH–DXHZ)

Disable time, DX high impedance following last data bit from

FSX high

2P+ 4

4P + 10

M29

td(FXL–DXV)

Delay time, FSX low to DX valid

2P + 4

4P + 10

† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

‡ P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU

clock frequency, use P = 2/300 MHz = 6.66 ns.

§ McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the

TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU592).

¶ T = BCLKX period = (1 + CLKGDV) * 2P

C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even

# FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

|| FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).

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