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TMS320VC5421 bảng dữ liệu(PDF) 73 Page - Texas Instruments

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TMS320VC5421 bảng dữ liệu(HTML) 73 Page - Texas Instruments

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Electrical Specifications
73
December 1999 − Revised October 2008
SPRS098D
5.9
Externally Generated Wait States
5.9.1 I/O Port Read and Write With Externally Generated Wait States
The following timing requirements table assumes testing over recommended operating conditions and
H = 0.5tc(CO) (see Figure 5−10 and Figure 5−11).
Table 5−14. Externally Generated Wait States Timing Requirements†
MIN
MAX
UNIT
tsu(RDY)
Setup time, READY before CLKOUT low
8
ns
th(RDY)
Hold time, READY after CLKOUT low
0
ns
tv(RDY)IOSTRB
Valid time, READY after IOSTRB low‡
3H−9
ns
th(RDY)IOSTRB
Hold time, READY after IOSTRB low‡
3H
ns
† The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states using
READY, at least two software wait states must be programmed.
‡ These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
tsu(RDY)
IOSTRB
READY
PPA[18:0]
CLKOUT
th(RDY)
Wait State Generated
by READY
Wait
States
Generated
Internally
tv(RDY)IOSTRB
th(RDY)IOSTRB
Figure 5−10. I/O Port Read With Externally Generated Wait States



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