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TMS320VC5421 bảng dữ liệu(PDF) 69 Page - Texas Instruments

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Electrical Specifications
69
December 1999 − Revised October 2008
SPRS098D
5.7
Ready Timing For Externally Generated Wait States
The following timing requirements table assumes testing over recommended operating conditions and
H = 0.5tc(CO) (see Figure 5−6 and Figure 5−7).
Table 5−10. Ready Timing Requirements for Externally Generated Wait States†
MIN
MAX
UNIT
tsu(RDY)
Setup time, READY before CLKOUT low
8
ns
th(RDY)
Hold time, READY after CLKOUT low
0
ns
tv(RDY)MSTRB Valid time, READY after MSTRB low‡
2H−8
ns
th(RDY)MSTRB Hold time, READY after MSTRB low‡
2H
ns
† The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY,
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
‡ These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT
MSTRB
READY
PPA[18:0]
CLKOUT
th(RDY)
th(RDY)MSTRB
tv(RDY)MSTRB
Wait State
Generated
by READY
Wait States
Generated Internally
tsu(RDY)
Figure 5−6. Memory Read With Externally Generated Wait States



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