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TMS320VC5421 bảng dữ liệu(PDF) 38 Page - Texas Instruments |
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TMS320VC5421 bảng dữ liệu(HTML) 38 Page - Texas Instruments |
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38 / 104 page ![]() Functional Overview 38 December 1999 − Revised October 2008 SPRS098D 3.7 Multichannel Buffered Serial Port (McBSP) The 5421 device provides high-speed, full-duplex serial ports that allow direct interface to other C54x/LC54x devices, codecs, and other devices in a system. There are six multichannel buffered serial ports (McBSPs) on board (three per subsystem). The McBSP provides: • Full-duplex communication • Double-buffer data registers, which allow a continuous data stream • Independent framing and clocking for receive and transmit In addition, the McBSP has the following capabilities: • Direct interface to: − T1/E1 framers − MVIP switching-compatible and ST-BUS compliant devices − IOM-2 compliant device − AC97-compliant device − Serial peripheral interface (SPI) • Multichannel transmit and receive of up to 128 channels • A wide selection of data sizes, including: 8, 12, 16, 20, 24, or 32 bits •µ-law and A-law companding • Programmable polarity for both frame synchronization and data clocks • Programmable internal clock and frame generation The 5421 McBSPs have been enhanced to provide more flexibility in the choice of the sample rate generator input clock source. On previous TMS320C5000 DSP platform devices, the McBSP sample rate input clock can be driven from one of two possible choices: the internal CPU clock , or the external CLKS pin. However, most C5000 DSP devices have only the internal CPU clock as a possible source because the CLKS pin is not implemented on most device packages. To accommodate applications that require an external reference clock for the sample rate generator, the 5421 McBSPs allow either the receive clock pin (BCLKR) or the transmit clock pin (BCLKX) to be configured as the input clock to the sample rate generator. This enhancement is enabled through two register bits: pin control register (PCR) bit 7 − enhanced sample clock mode (SCLKME), and sample rate generator register 2 (SRGR2) bit 13 − McBSP sample rate generator clock mode (CLKSM). SCLKME is an addition to the PCR contained in the McBSPs on previous C5000 devices. The new bit layout of the PCR is shown in Figure 3−8. For a description of the remaining bits, see TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature number SPRU302). TMS320C5000 and C5000 are trademarks of Texas Instruments. |
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