TMS320VC5421 datasheet(57/104 Pages) TI1

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Functional Overview

December 1999 − Revised October 2008

SPRS098D

3.13 Interrupts

Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3−23.

Table 3−23. 5421 Interrupt Locations and Priorities for Each DSP Subsystem

NAME

LOCATION

PRIORITY

FUNCTION

NAME

DECIMAL

HEX

PRIORITY

FUNCTION

RS, SINTR

Reset (Hardware and Software Reset)

NMI, SINT16

Nonmaskable Interrupt

SINT17

—

Software Interrupt #17

SINT18

—

Software Interrupt #18

SINT19

—

Software Interrupt #19

SINT20

—

Software Interrupt #20

SINT21

—

Software Interrupt #21

SINT22

—

Software Interrupt #22

SINT23

—

Software Interrupt #23

SINT24

—

Software Interrupt #24

SINT25

—

Software Interrupt #25

SINT26

—

Software Interrupt #26

SINT27

—

Software Interrupt #27

SINT28

—

Software Interrupt #28

SINT29

—

Software Interrupt #29

SINT30

—

Software Interrupt #30

INT0, SINT0

External User Interrupt #0

INT1, SINT1

External User Interrupt #1

INT2, SINT2

Reserved

TINT, SINT3

External Timer Interrupt

BRINT0, SINT4

BSP #0 Receive Interrupt

BXINT0, SINT5

BSP #0 Transmit Interrupt

BRINT2, DMAC0

BSP #2 Receive Interrupt or DMA Channel 0

BXINT2, DMAC1

BSP #2 Receive Interrupt or DMA Channel 1

INT3, SINT8

Reserved

HPINT, SINT9

100

HPI Interrupt (from DSPINT in HPIC)

BRINT1, DMAC2

104

BSP #1 Receive Interrupt or DMA Channel 2

BXINT1, DMAC3

108

BSP #1 transmit Interrupt or DMA channel 3

DMAC4, SINT12

112

DMA Channel 4

DMAC5, SINT13

116

DMA Channel 5

IPINT, SINT14

120

Interprocessor Interrupt

—

124−127

7C−7F

—

Reserved

The interprocessor interrupt (IPINT) bit of the interrupt mask register (IMR) and the interrupt flag register (IFR)

allows the subsystem to perform interrupt service routines based on the other subsystem activity. Incoming

IPINT interrupts are latched in IFR.14. Generating an interprocessor interrupt is performed by writing a “1” to

the IPIRQ field of the bank-switching control register (BSCR). Subsequent interrupts must first clear the

interrupt by writing “0” to the IPIRQ field. Figure 3−21 shows the bit layout of the IMR and the IFR. Table 3−24

describes the bit functions.

For example, if subsystem A is required to notify subsystem B of a completed task, subsystem A must write

a “1” to the IPIRQ field to generate a IPINT interrupt on subsystem B. On subsystem B, the IPINT interrupt

is latched in IFR.14. Figure 5 shows the bit layout of the BSCR and Table 6 describes the bit functions.

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