TMS320VC5421 datasheet(37/104 Pages) TI1

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Functional Overview

December 1999 − Revised October 2008

SPRS098D

HOST

HPI-16

Data[15:0]

HD[15:0]

R/W

HR/W

Data strobes

HDS1, HDS2, HCS

HRDY

Ready

HPID[15:0]

DMA

54x

CPU

Address[n:0]

HA[n :0]

Figure 3−7. Interfacing to the HPI-16 in Non-Multiplexed Mode

3.6.7 Other HPI16 System Considerations

3.6.7.1

Operation During IDLE

The HPI16 can continue to operate during IDLE1 or IDLE2 by using special clock management logic that turns

on relevant clocks to perform a synchronous memory access, and then turns the clocks back off to save power.

The DSP CPU does not wake up from the IDLE mode during this process.

3.6.7.2

Downloading Code During Reset

The HPI16 can download code while the DSP is in reset. However, the system provides a pin (HPIRS) that

provides a way to take the HPI16 module out of reset while leaving the DSP in reset. The maximum HPI16

data rate is 33 MBps assuming no other DMA activity (100-MIPS DSP subsystem).

3.6.7.3

Performance Issues

On the 5421, the use of SELA/B is optional for access to all on-chip memory. However, with both the 5420 and

5421 implementation using two separate subsystems (subchips), the SELA/B pin is used to select the specific

HPI16 used to access memory.

SELA/B PIN

SUBSYSTEM

Accesses to memory contained inside the same subsystem as the selected HPI16 will be faster. For accesses

to an HPI16 in a subsystem different than the memory being addressed, reads take an additional six cycles

and writes an extra five cycles. Therefore, for performance reasons, it is best to additionally decode SELA/B.

TMS320VC5421 bảng dữ liệu(PDF) 37 Page - Texas Instruments