TMS320VC5421 datasheet(68/104 Pages) TI1

68 / 104 page

Electrical Specifications

December 1999 − Revised October 2008

SPRS098D

5.6.2 Memory Write

The following switching characteristics table assumes testing over recommended operating conditions with

MSTRB = 0 and H = 0.5tc(CO) (see Figure 5−5).

Table 5−9. Memory Write Switching Characteristics

PARAMETER

MIN

MAX

UNIT

td(CLKH-A)

Delay time, CLKOUT high to address valid†‡

− 1

td(CLKL-A)

Delay time, CLKOUT low to address valid†§

−1

td(CLKL-MSL)

Delay time, CLKOUT low to MSTRB low

−1

td(CLKL-D)W

Delay time, CLKOUT low to data valid

td(CLKL-MSH)

Delay time, CLKOUT low to MSTRB high

− 1

td(CLKH-RWL) Delay time, CLKOUT high to R/W low

td(CLKH-RWH) Delay time, CLKOUT high to R/W high

td(RWL-MSTRBL) Delay time, R/W low to MSTRB low

H − 2

H + 2

th(A)W

Hold time, address valid after CLKOUT high†‡

−1

th(D)MSH

Hold time, write data valid after MSTRB high

H − 3

H +3§

tw(SL)MS

Pulse duration, MSTRB low§

2H−4

tsu(A)W

Setup time, address valid before MSTRB low†

2H−4

tsu(D)MSH

Setup time, write data valid before MSTRB high

2H−5

2H+5§

† Address, PS, and DS timings are all included in timings referenced as address.

‡ In the case of a memory write preceded by a memory write

§ In the case of a memory write preceded by an I/O cycle

PS, DS

R/W

MSTRB

PPD[15:0]

PPA[18:0]

CLKOUT

td(CLKH-RWH)

th(A)W

td(CLKL-MSH)

tsu(D)MSH

td(CLKL-D)W

tw(SL)MS

tsu(A)W

td(CLKL-MSL)

th(D)MSH

td(CLKL-A)

td(CLKH-RWL)

td(RWL-MSTRBL)

td(CLKH-A)

Figure 5−5. Memory Write (MSTRB = 0)

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