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PM8313 bảng dữ liệu(PDF) 98 Page - PMC-Sierra, Inc |
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PM8313 bảng dữ liệu(HTML) 98 Page - PMC-Sierra, Inc |
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98 / 192 page ![]() PM8313 D3MX DATA SHEET PMC-920702 ISSUE 5 M13 MULTIPLEXER 88 Register 25H: RFDL TSB Interrupt Control/Status Bit Type Function Default Bit 7 Unused X Bit 6 Unused X Bit 5 Unused X Bit 4 Unused X Bit 3 Unused X Bit 2 R/W INTC1 0 Bit 1 R/W INTC0 0 Bit 0 R INT 0 INTC1, INTC0: The INTC1 and INTC0 bits control when an interrupt is asserted based on the number of received data bytes in the FIFO as follows: INTC1 INTC0 Description 0 0 Disable interrupts (All sources) 0 1 Enable interrupt when FIFO receives data 1 0 Enable interrupt when FIFO has 2 bytes of data 1 1 Enable interrupt when FIFO has 3 bytes of data INT: The INT bit reflects the status of the external RDLINT interrupt unless the INTC1 and INTC0 bits are set to disable interrupts. In that case, the RDLINT output is forced to 0 and the INT bit of the Interrupt Control/Status register will reflect the state of the internal interrupt latch. FIFO: In addition to the FIFO fill status, interrupts are also generated for EOM (end of message), OVR (FIFO overrun), detection of the abort sequence while not |
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