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PM8313 bảng dữ liệu(PDF) 36 Page - PMC-Sierra, Inc |
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PM8313 bảng dữ liệu(HTML) 36 Page - PMC-Sierra, Inc |
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36 / 192 page ![]() PM8313 D3MX DATA SHEET PMC-920702 ISSUE 5 M13 MULTIPLEXER 26 Pin Name Type Pin No. Function TDLSIG/ TDLUDR I/O 205 The transmit data link (TDLSIG) signal is active when an external HDLC receiver is selected (the TEXHDLC bit in the corresponding Master HDLC Configuration Register is a logic 1). The TDLSIG signal carries bits to be inserted in the three C-bits in M-subframe #5 by the DS3 transmitter. TDLSIG is ignored when C-bit parity mode is not enabled. TDLSIG is sampled on the rising edge of the TDLCLK signal. The transmit data link underrun (TDLUDR) signal is active when the internal HDLC receiver is selected (the TEXHDLC bit in the corresponding Master HDLC Configuration Register is a logic 0). TDLUDR is asserted when the internal HDLC transmitter underruns. TDLUDR is deasserted by writing to the XFDL Interrupt Status Register. By default TDLUDR is an active low open-drain output, but can be configured as active high. Upon a reset, the TEXHDLC bit a logic 1, thus, the pin is configured as an input, TDLSIG. Typically, TDLUDR would be connected to the supervising microprocessor when an external DMA is used, signaling the microprocessor that a severe error has occurred causing the transmit buffer to underrun. In this case the TDLUDR is configured as an active-low open drain output and wired-ORed with the INTB output. |
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