PM8313 datasheet(85/192 Pages) PMC

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PM8313 D3MX

DATA SHEET

PMC-920702

ISSUE 5

M13 MULTIPLEXER

DLCV:

The DLCV controls the insertion of a single line code violation in the outgoing

DS3 stream. When the DLCV is set to logic 1, a line code violation is inserted

by generating an incorrect polarity of violation in the next B3ZS signature.

The data being transmitted must therefore contain periods of three

consecutive zeros in order for the line code violation to be inserted. For

example line code violations may not be inserted when transmitting AIS, but

will be inserted when transmitting the idle signal. This bit is automatically

cleared upon insertion of the line code violation.

DLOS:

The DLOS controls the insertion of loss of signal in the outgoing DS3 stream.

When DLOS is set to a logic 1, the data on outputs TPOS, TNEG, and TDAT

are forced to continuous zeros.

10.1

DS3 PMON Registers

Latching Performance Data

The DS3 Performance Monitor (PMON) data registers (16H-1FH) are updated by

the rising edge of an internal transfer clock signal. The time between successive

rising edges of the transfer clock determines the accumulation interval, which is

nominally one second. A microprocessor write to any of the PMON count data

registers causes a transfer clock and an update of the PMON data registers.

Only one register location need be written to cause an update of all PMON data

registers. The PMON is loaded with new performance data within 3 ROHCLK

periods of the trailing edge of a microprocessor write. With ROHCLK at its

nominal frequency of 526 kHz, the PMON registers should not be read until 6 µs

have elapsed since the microprocessor write was performed. The data contained

in the holding registers are subsequently read from the PMON registers by the

microprocessor. The loading is synchronized to the internal event timing so that

no events are missed.

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