PM8313 datasheet(95/192 Pages) PMC

95 / 192 page

PM8313 D3MX

DATA SHEET

PMC-920702

ISSUE 5

M13 MULTIPLEXER

Bit

Type

Function

Default

Bit 7

Unused

Bit 6

Unused

Bit 5

Unused

Bit 4

Unused

Bit 3

Unused

Bit 2

Unused

Bit 1

INT

Bit 0

R/W

UDR

INT:

The INT bit indicates when the XFDL TSB is ready to accept a new data byte

for transmission. The INT bit is set to a logic 1 when the previous byte in the

Transmit Data register has been loaded into the parallel to serial converter

and a new byte can be written into the Transmit Data register. The INT bit is

set to a logic 0 while new data is in the Transmit Data register. The INT bit is

not disabled by the INTE bit in the configuration register.

UDR:

The UDR bit indicates when the XFDL TSB has underrun the data in the

Transmit Data register. The UDR bit is set to a logic 1 if the parallel to serial

conversion of the last byte in the Transmit Data register has completed before

the new byte was written into the Transmit Data register. Once an underrun

has occurred, the XFDL transmits an ABORT, followed by a flag, and waits to

transmit the next valid data byte. If the UDR bit is still set after the

transmission of the flag the XFDL will continuously transmit the all-ones idle

pattern. The UDR bit can only be cleared by writing a logic 0 to the UDR bit

position in this register.

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