PM8313 datasheet(65/192 Pages) PMC

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PM8313 D3MX

DATA SHEET

PMC-920702

ISSUE 5

M13 MULTIPLEXER

Bit

Type

Function

Default

Bit7

R/W

EXD2CLK

Bit6

R/W

BYP7

Bit5

R/W

BYP6

Bit4

R/W

BYP5

Bit3

R/W

BYP4

Bit2

R/W

BYP3

Bit1

R/W

BYP2

Bit0

R/W

BYP1

The Master Bypass Configuration Register is provided at D3MX read/write

address 02H.

BYP[7:1]:

The BYP[7:1] bits allow for each of the seven MX12 blocks to be individually

bypassed so that an external DS2 may be multiplexed and demultiplexed

directly without the intermediate M12 multiplexing. If BYP[n] is a logic 1, the

following applies:

1. A nominally 6.312 MHz clock is expected on TD1CLK(4n).

2. A data stream synchronous to TD1CLK(4n) is expected on TD1DAT(4n).

3. The clocks on TD1CLK(4n-1), TD1CLK(4n-2) and TD1CLK(4n-3) have no

effect.

4. The data streams on TD1DAT(4n-1), TD1DAT(4n-2) and TD1DAT(4n-3) are

ignored.

5. A nominally 6.312 MHz clock is presented on RD1CLK(4n).

6. A data stream synchronous to RD1CLK(4n) is presented on RD1DAT(4n).

7. The signals on RD1CLK(4n-1), RD1CLK(4n-2), RD1CLK(4n-3),

RD1DAT(4n-1), RD1DAT(4n-2) and RD1DAT(4n-3) are always low.

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