PM8313 datasheet(62/192 Pages) PMC

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PM8313 D3MX

DATA SHEET

PMC-920702

ISSUE 5

M13 MULTIPLEXER

Bit

Type

Function

Default

Bit7

DS3RCACT

Bit6

DS3TCACT

Bit5

DS2TCACT

Bit4

Unused

Bit3

Unused

Bit2

Unused

Bit1

Unused

Bit0

R/W

RESET

The Master Reset Register is provided at D3MX read/write address 00H.

RESET:

The RESET bit implements a software reset. If the RESET bit is a logic 1, the

entire D3MX is held in reset. This bit is not self-clearing; therefore, a logic 0

must be written to bring the D3MX out of reset. Holding the D3MX in a reset

state effectively puts it into a low power, stand-by mode. A hardware reset

clears the RESET bit, thus deasserting the software reset.

DS3RCACT:

The DS3 Receive Clock Activity (DS3RCACT) bit indicates at least one low to

high transition has occurred on the RCLK input since the last read of this

input and is cleared to a logic 0 by a read of this register.

DS3TCACT:

The DS3 Transmit Clock Activity (DS3TCACT) bit indicates at least one low to

high transition has occurred on the TICLK input since the last read of this

input and is cleared to a logic 0 by a read of this register.

DS2TCACT:

The DS2 Transmit Clock Activity (DS2TCACT) bit indicates at least one low to

high transition has occurred on the TD2CLK input since the last read of this

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