PM8313 datasheet(76/192 Pages) PMC

76 / 192 page

PM8313 D3MX

DATA SHEET

PMC-920702

ISSUE 5

M13 MULTIPLEXER

Bit

Type

Function

Default

Bit 7

R/W

VCLK_IOTST

Bit 6

Unused

Bit 5

Unused

Bit 4

PMCTST

Bit 3

DBCTRL

Bit 2

R/W

IOTST

Bit 1

HIZDATA

Bit 0

R/W

HIZIO

The Master Test Register is provided at D3MX read/write address 07H.

This register is used to select D3MX test features. All bits, except for PMCTST,

are reset to zero by a hardware reset of the D3MX; a software reset of the D3MX

does not affect the state of the bits in this register.

VCLK_IOTST:

The VCLK_IOTST bit replaces the RCLK/VCLK input as the test clock when

the IOTST bit is a logic 1. Some sense points require a rising edge on the

test clock to clock in the value on the pin. This bit satisfies the requirement

without needing the RCLK/VCLK input to toggle.

PMCTST:

The PMCTST bit is used to configure the D3MX for PMC's manufacturing

tests. When PMCTST is set to logic 1, the D3MX microprocessor port

becomes the test access port used to run the PMC "canned" manufacturing

test vectors. The PMCTST bit is logically "ORed" with the IOTST bit, and can

only be cleared by setting CSB to logic 1.

DBCTRL:

The DBCTRL bit is used to pass control of the data bus drivers to the CSB

pin while IOTST is a logic 1. When the DBCTRL bit is set to logic 1, the CSB

pin controls the output enable for the data bus. While the DBCTRL bit is set,

holding the CSB pin high causes the D3MX to drive the data bus and holding

the CSB pin low tri-states the data bus. The DBCTRL bit overrides the

HIZDATA bit. The DBCTRL bit is used to measure the drive capability of the

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