DS3134 datasheet(153/203 Pages) DALLAS

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DS3134

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Bit 5 / VGA Control (VGA). This read only bit is forced to zero by the device to indicate that it is not a

VGA compatible device.

Bit 6 / Parity Error Response Control (PARC). This read/write bit controls whether or not the device

should ignore parity errors. When this bit is set to zero, the device will ignore any parity errors that it

detects and continue to operate normally. When this bit is set to one, the device must act on parity errors.

This bit is forced to zero when a hardware reset is initiated via the PRST* pin.

0 = ignore parity errors

1 = act on parity errors

Bit 7 / Address Stepping Control (STEPC). This read only bit is forced to zero by the device to indicate

that it is not capable of address/data stepping.

Bit 8 / PCI System Error Control (PSEC). This read/write bit controls whether or not the device

should enable the PSERR* output pin. When this bit is set to zero, the device will disable the PSERR*

pin and when this bit is set to one, the device will enable the PSERR* pin. This bit is forced to zero when

a hardware reset is initiated via the PRST* pin.

0 = disable the PSERR* pin

1 = enable the PSERR* pin

Bit 9 / Fast Back-to-Back Master Enable (FBBEN). This read only bit is forced to zero by the device

to indicate that it is not capable of generating fast back-to-back transactions to different agents.

Bits 10 to 15 / Reserved. These read only bits are forced to zero by the device.

STATUS BITS

The upper word in the PCMD0 register is the Status portion, which report events as they occur. As

mentioned earlier, reads of the Status portion occur normally but writes are unique in that bits can only be

reset (i.e. forced to zero). This occurs when a one is written to a bit position. Writes with a zero to a bit

position have no affect. This allows individual bits to be reset.

Bits 16 to 20 / Reserved. These read only bits are forced to zero by the device.

Bit 21 / 66 MHz Capable (66 MHz). This read only bit is forced to zero by the device to indicate that it

is not capable of running at 66 MHz.

Bit 22 / User Definable Features Capable (UDF). This read only bit is forced to zero by the device to

indicate that it does not support User Definable Features.

Bit 23 / Fast Back-to-Back Capable Target (FBBCT). This read only bit is forced to one by the device

to indicate that it is capable of accepting fast back-to-back transactions when the transactions are not from

the same agent.

Bit 24 / PCI Parity Error Reported (PARR). This read/write bit will be set to a one when the device is

a bus master and detects or asserts the PPERR* signal when the PARC command bit is enabled. This bit

can be reset (set to zero) by the Host by writing a one to this bit.

0 = no parity errors have been detected

1 = parity errors detected

DS3134 bảng dữ liệu(PDF) 153 Page - Dallas Semiconductor