CP3SP33SMSSLASHNOPB datasheet(320/407 Pages) TI1

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Peripheral Bus Clock

PRESET

Watchdog Clock

CP3SP33

SNOSCW5 – MAY 2013

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T0INTE

The Timer T0 Interrupt Enable bit enables an interrupt to the CPU each time the Timer T0

count reaches zero. When this bit is clear, Timer T0 interrupts are disabled.

0 – Timer T0 interrupts disabled.

1 – Timer T0 interrupts enabled.

WDLTD

The Watchdog Last Touch Delay bit is set when either WDCNT or WDSDM is written and the

data transfer to the Watchdog is in progress (see WDCNT and WDSDM register description).

When clear, it is safe to switch to Power Save mode.

0 – No data transfer to the Watchdog is in progress, safe to enter Power Save mode.

1 – Data transfer to the Watchdog in progress.

FRZT0E

The Freeze Timer 0 Enable bit controls whether Timer 0 is stopped in Freeze mode. If this bit

is set, the Timer 0 is frozen (stopped) when the Freeze input to the TWM is asserted. If the

FRZT0E bit is clear, only the Watchdog timer is frozen by asserting the Freeze input signal.

After reset, this bit is clear.

0 – Timer T0 unaffected by Freeze mode.

1 – Timer T0 stopped in Freeze mode.

31.4.5 Watchdog Count Register (WDCNT)

The WDCNT register is a byte-wide, write-only register that holds the value that is loaded into the

Watchdog counter each time the Watchdog is serviced. The Watchdog is started by the first write to this

this register is initialized to 0Fh.

PRESET

The WDCNT register operates from PCLK Clock, not Slow Clock. Because the rest of the Watchdog

service mechanism operates from Slow Clock, there is a small amount of latency between the write to the

WDCNT register and the actual service of the Watchdog. Due to this latency it is not recommended to use

small PRESET values. In Power Save mode, it is even more important because the latency time (in clock

cycles) is even longer than in Active mode. The minimum PRESET value must be large enough to satisfy

this latency, which is expressed in this relation:

(13)

31.4.6 Watchdog Service Data Match Register (WDSDM)

The WSDSM register is a byte-wide, write-only register used for servicing the Watchdog. When this type

of servicing is enabled (TWCFG.WDSDME = 1), the Watchdog is serviced by writing the value 5Ch to the

WSDSM register. Each such servicing reloads the Watchdog counter with the value previously written to

the WDCNT register. Writing any data other than 5Ch triggers a Watchdog error. Writing to the register

more than once in one Watchdog clock cycle also triggers a Watchdog error signal. If this type of servicing

is disabled (TWCFG.WDSDME = 0), any write to the WSDSM register is ignored.

RSTDATA

31.5 Watchdog Programming Procedure

The highest level of protection against software errors is achieved by programming and then locking the

Watchdog registers and using the WDSDM register for servicing. This is the procedure:

1. Write the desired values into the TWM Clock Prescaler register (TWCP) and the TWM Timer 0 register

(TWMT0) to control the T0IN and T0OUT clock rates. The frequency of T0IN can be programmed to

any of six frequencies ranging from 1/32 × fSLCLK to fSLCLK. The frequency of T0OUT is equal to the

320

Timing and Watchdog Module

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