CP3SP33SMSSLASHNOPB datasheet(319/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

31.4.2 Timer and Watchdog Clock Prescaler Register (TWCP)

The TWCP register is a byte-wide, read/write register that specifies the prescaler value used for dividing

the low-frequency clock to generate the T0IN clock. At reset, the non-reserved bits of the register are

cleared. The register format is shown below.

3M M2

Reserved

MDIV

Main Clock Divide. This 3-bit field defines the prescaler factor used for dividing the low speed

device clock to create the T0IN clock. The allowed 3-bit values and the corresponding clock

divisors and clock rates are listed below.

Clock Divisor

MDIV

T0IN Frequency

(fSCLK = 32.768 kHz)

000

32.768 kHz

001

16.384 kHz

010

8.192 kHz

011

4.096 kHz

100

2.056 kHz

101

1.024 kHz

Other

Reserved

N/A

31.4.3 TWM Timer 0 Register (TWMT0)

The TWMT0 register is a 16-bit, read/write register that de- fines the T0OUT interrupt rate. At reset,

TWMT0 register is initialized to FFFFh. The register format is shown below.

PRESET

The Timer T0 Preset field holds the value used to reload Timer T0 on each underflow.

Therefore, the frequency of the Timer T0 interrupt is the frequency of T0IN divided by

(PRESET+1). The allowed values of PRESET are 0001h through FFFFh.

31.4.4 TWMT0 Control and Status Register (T0CSR)

The T0CSR register is a byte-wide, read/write register that controls Timer T0 and shows its current status.

At reset, the non-reserved bits of the register are cleared. The register format is shown below.

Reserved

FRZT0E

WDLTD

T0INTE

RST

The Restart bit is used to reset Timer T0. When this bit is set, it forces the timer to reload the

value in the TWMT0 register on the next rising edge of the selected input clock. The RST bit

is reset automatically by the hardware on the same rising edge of the selected input clock.

Writing a 0 to this bit position has no effect. At reset, the non-reserved bits of the register are

cleared.

0 – Writing 0 has no effect.

1 – Writing 1 resets Timer T0.

The Terminal Count bit is set by hardware when the Timer T0 count reaches zero and is

cleared when software reads the T0CSR register. It is a read-only bit. Any data written to this

bit position is ignored.

0 – Timer T0 did not count down to 0.

1 – Timer T0 counted down to 0.

Timing and Watchdog Module

319

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