CP3SP33SMSSLASHNOPB datasheet(316/407 Pages) TI1

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5-Bit Prescaler Counter

(TWCP)

REAL TIME TIMER (T0)

WATCHDOG

Restart

Underflow

Slow

Clock

T0LINT

(to ICU)

T0OUT

(to Multi-Input-

Wake-Up)

WDERR

Watchdog Error

16-Bit Timer

(Timer0)

WATCHDOG

Timer

WATCHDOG

Service

Logic

TWW/MT0 Register

T0CSR Contrl. Reg.

WDSDM

WDCNT

DS080

T0IN

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

Figure 31-1. Timing and Watchdog Module Block Diagram

When the counter reaches zero, an internal timer signal called T0OUT is set for one T0IN clock cycle.

This signal sets the TC bit in the TWMT0 Control and Status Register (T0CSR). It also asserts an interrupt

(IRQ70), when enabled by the T0CSR.T0INTE bit. T0OUT is also an input to the MIWU (see Section 17),

so an edge-triggered interrupt is also available through this alternative mechanism.

If software loads the TWMT0 register with a new value, the timer uses that value the next time that it

reloads the 16-bit timer register (in other words, after reaching zero). Software can restart the timer at any

time (on the very next edge of the T0IN clock) by setting the Restart (RST) bit in the T0CSR register. The

T0CSR.RST bit is cleared automatically upon restart of the 16-bit timer.

NOTE

To enter Power Save or Idle mode after setting the T0CSR.RST bit, software must wait for

the reset operation to complete before performing the switch.

31.3 Watchdog Operation

The Watchdog is an 8-bit down counter that operates on the rising edge of a specified clock source. At

reset, the Watchdog is disabled; it does not count and no Watchdog signal is generated. A write to either

the Watchdog Count (WDCNT) register or the Watchdog Service Data Match (WDSDM) register starts the

counter. The Watchdog counter counts down from the value programmed in the WDCNT register. Once

started, only a reset can stop the Watchdog from operating.

The Watchdog can be programmed to use either T0OUT or T0IN as its clock source (the output and input

of Timer T0, respectively). The TWCFG.WDCT0I bit selects the clock source.

Software must periodically service the Watchdog. There are two ways to service the Watchdog, the choice

depending on the programmed value of the WDSDME bit in the Timer and Watchdog Configuration

(TWCFG) register.

If the TWCFG.WDSDME bit is clear, the Watchdog is serviced by writing a value to the WDCNT register.

The value written to the register is reloaded into the Watchdog counter. The counter then continues

counting down from that value.

316

Timing and Watchdog Module

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